1. Field of the Invention
The present invention relates in general to a semiconductor process. More particularly, it relates to a simplified process for integrating an alignment mark and a trench device to reduce fabrication cost.
2. Description of the Related Art
Lithography is one of most important processes for fabricating semiconductor integrated circuits. Lithography is used in the transfer of a pattern onto a thin film or the fabrication of a mask for ion implantation. In general, lithography is conducted many times in the production of is semiconductor circuits. In a lithography step, however, one critical factor is pattern alignment. When a wafer is processed to form patterns in the different thin films deposited thereon, the wafer must be properly aligned relative to the previous pattern. Conventionally, an alignment mark (AM) is used for alignment before carrying out photo-exposure.
In general, alignment marks are formed outside the device region, such as the scribe line of a wafer, at the same time as a thin film such as an insulating layer or a conductive layer is patterned. FIGS. 1a to 1d are cross-sections showing a conventional process for integrating an alignment mark and a trench device. First, in FIG. 1a, a substrate 100, such as a silicon wafer, is provided. The substrate 100 has a device region 10 and an alignment mark region 20 which is at the scribe line of the wafer 100.
Next, a patterned masking layer 105 is formed on the substrate 100. The patterned masking layer 105 can be composed of a pad oxide layer 102 and a thicker overlying silicon nitride layer 104. Next, the substrate 100 is etched using the patterned masking layer 105 as an etch mask to form deep trenches 110a and 110b therein. The deep trench 110a is on the device region 10 and the trench 110b having a width larger than the deep trench 110a is on the alignment mark region 20.
Next, trench capacitors 118a and 118b are respectively formed in the lower portion of the deep trenches 110a and 110b. The trench capacitor 118a includes a top plate 116a, a capacitor dielectric layer 114a, and a bottom plate 112a. Also, the trench capacitor 118b includes a top plate 116b, a capacitor dielectric layer 114b, and a bottom plate 112b. Next, collar insulating layers 117a and 117b are respectively formed on the trench capacitors 118a and 118b and over the sidewall of the deep trenches 110a and 110b. Thereafter, conductive layers 120a and 120b, such as polysilicon, are respectively formed in the deep trenches 110a and 110b, which have a height substantially equal to the collar insulating layers 117a and 117b. 
Next, a conductive layer 122, such as polysilicon, is formed on the masking layer 105 and fills in the deep trenches 110a and 110b. 
Next, in FIG. 1b, chemical mechanical polishing (CMP) is performed on the conductive layer 122 to respectively leave a portion of the conductive layers 122a and 122b in the deep trenches 110a and 110b. 
Next, in FIG. 1c, the conductive layers 122a and 122b are etched to leave a portion of the conductive layers 124a and 124b in the deep trenches 110a and 110b, respectively. The conductive layer 120a and the remaining conductive layer 124a in the deep trench 110a are used as a wiring layer for the trench capacitor 118a. In addition, the trench capacitor 118b, the conductive layer 120b, and the remaining conductive layer 124b are used as an alignment mark.
Since the trench capacitor 118b and the conductive layers 120b and 124b are formed in the deep trench 110b, the step height of the substrate 100 on the alignment mark region 20 is reduced, lowering the image contrast of the alignment mark.
Accordingly, in FIG. 1d, a patterned photoresist layer (not shown) is formed on the masking layer 105 by lithography to completely cover the deep trench 110a and expose the deep trench 110b only. Thereafter, the conductive layer 124b is completely removed and then the underlying conductive layer 120b and the collar insulating layer 117b are partially removed by etching using the patterned photoreist layer as a mask to leave a portion of the conductive layer 120c and the collar insulating layer 117c, thereby increasing the step height of the substrate 100 on the alignment mark region 20. However, such a process is complex, thus increasing fabrication cost and the time required thereby.
Accordingly, an object of the present invention is to provide a novel process for integrating an alignment mark and a trench device, thereby simplifying the process to reduce fabrication cost and time and increase throughput.
According to the object of the invention, a process for integrating an alignment mark and a trench device are provided. First, a substrate having first and second trenches is provided, wherein the second trench used as the alignment mark is wider than the first trench. Next, the trench device is formed in each of the low portions of the first and second trenches, and then a first conductive layer is formed on the trench device in each of the first and second trenches. Thereafter, a second conductive layer is formed overlying the substrate filling in the first trench and is simultaneously and conformably formed over the inner surface of the second trench. Finally, the second conductive layer and a portion of the first conductive layer in the second trench are removed and simultaneously leave a portion of the second conductive layer in the first trench by an etch back process, wherein the etch back process employs chemical mechanic polishing to remove the second conductive layer overlying the substrate.
Moreover, the first and second conductive layers can be a polysilicon layer, which have a thickness of about 2000xc3x85 to 4000xc3x85.